• Responsible for DFT feature and VerifPlan setup 
• DFT area work include Jtag ,SCAN, Boundary SCAN, MBIST and Analog 
• Develop test DFT cases and procedure
• Responsible to use and maintain dft and verification flow
• Generate test vectors and post silicon validation

• BSEE, MSEE is preferred
• Student will graduate in 2012 is preferred.
• Strong logic design and verification back ground 
• Possess knowledge of DFT (scan insertion, Mbist, JTAG and etc.) 
• Skilled in Perl/tcl, programming 
• Working knowledge in C/C++, makefile is a plus
• Prefer to have experience in logic simulators and debug tools (vcs, ncsim, verdi and etc.) 
• Prefer in verilog HDL 
• Problem solving and analytical skills

• Design, verify, debug and optimize the state-of-the-art GPU ASIC under some guidance;
• Developing tools to improve work efficiency

• Undergraduate students majoring in EE;
• Work at least 4 days/week
• Proactive and persistent. Strong problem solving skills. Willing to work on open ended issues. Team player;
• Good communication skills. Excellent oral and verbal English.
• Strong knowledge in Verilog HDL
• Experience of working in Linux/Unix environment
• Hands-on programming skills in Perl, C/C++.
• Experience in simulation, synthesis tools is a plus.

• ASIC Design for graphics and video processors.
• Micro-architecture definition; working closely with video / graphics and system architects.
• RTL design, verification, emulation, synthesis, timing, and silicon bring-up.

• MS in EE or related area
• Versed in verilog programming, familiar with all aspects of the front-end ASIC design flow
• Strong programming skills in C/C++, PERL preferred.
• Fluent in English speaking and writing
• Previous experiences on video codecs, like H.264/MPEG-2/VC1/VP8 is a huge plus.

Job Title: Mask Layout Design Intern
Location: China, Shanghai
Department: GPU

Job Description:

This position’s responsibilities will focus on custom layout design in 28nm, 20nm, or below process; Layout quality control and verification; Layout version control and release. Main projects include compiled RAM cells and STD cells with various infrastructures. You will work with highly talented, experienced and dedicated designers both in China and America

• BS or above in Electronics, Microelectronics or related fields
• Basic knowledge of semiconductor physics and mask layout design
• Good working knowledge of Unix required
• Good command of written and spoken English
• Rich imagination in tri-dimensional graphics--(plus)
• Experience of using common industry standard tools likes Virtuoso, Hercules/Calibre--(plus)
• Be familiar with schematic driven layout concept and constraints--(plus)

Job Title: Circuit Design Intern
Location: China, Shanghai
Department: GPU

Job Description:

• High performance, low power custom digital circuit design for graphics processors.
• Circuit architecting, simulation and characterization of custom design circuit.
• Logic equivalence checking and transistor level function verification.
• Participating in building CAD flow for circuit design.
• Layout floor planning and supervision.

Requirement:

• BSEE minimum, MSEE preferred.
• Strong background in deep submicron CMOS process and device.
• Good knowledge in high speed digital circuit design techniques.
• Understanding of on-chip inter connect and signal integrity.
• Experience in circuit simulation, schematic capture and layout verification CAD tools.
• Must be a team player with effective written and verbal communication skills.
• Must be able to learn quickly and work independently.
• Working 4 or more days one week is preferred.

Job Title: Circuit Design Intern (CAD)
Location: China, Shanghai
Department: GPU
Job Description/Qualifications:

As a CAD engineer in custom circuit design team, this person will develop/maintain CAD methodologies and flow for high-performance low-power circuit design, and contribute to NVIDIA's state-of-art products.

Job Description:

• Develop design methodologies and flow automation for custom circuit design and verification.
• Provide internal tools and solution for design implementation and process migration.
• Participate in problem definition, feasibility study and design engineering.
• Establish and maintain design environment and tools.

Requirement:

• Master’s degree (in EE/CS) anticipated in 2012.
• Strong programming skills in Perl/Shell/Tcl,etc.
• Good knowledge in deep submicron CMOS process and device.
• Experience in circuit design tools.
• Must be a team player with effective written and verbal communication skills.
• Must be able to learn quickly and work independently.

Job Title: GPU Architect Intern
Location: China, Shanghai
Department: GPU

Job Description:

• We are looking for world class programmers to develop the core infrastructure for modeling, analysis, verification and debugging in the development of large scale graphics chips, which enables NVIDIA's driver stack, applications, tests and studies to all run unchanged on all functional, diagnostic, and performance models, simulations, emulations and silicon for all of NVIDIA's graphics chips.
• The candidates will work with a group of architects to design and develop proprietary internal tools for the visualization, analysis, debug and verification of tests on various functional and performance simulations for future products.
• - The candidates will have opportunities to get involved in cutting-edge GPGPU applied architecture design, verification and optimization, including porting commercial applications to test bench, finding out performance hotspots and data mining for performance analysis.

Requirement:

• Bachelor's Degree candidate majoring in CS/EE/Mathematics or relevant fields. Graduate in 2012 preferred. Higher education is preferred.
• Strong C/C++ programming ability. Scripting language (Perl, Python, Ruby) experience is a plus.
• Well organized problem solving capability and communication skills.
• Strong software debugging capability and experiences.
• Available to work at least 4 days/week.
• Excellent English writing for engineering documentation, English oral well enough to attend meetings.
• Experience in the following areas is a plus:
• Microprocessor architecture design & verification
• 3D graphics (d3d or OpenGL) application development
• Multimedia (video, image processing, visualization) application development
• System level programming experience in OS, compiler, driver, tools, virtual memory system, etc.
• Parallel computing/CUDA/OpenCL/HPC development

Job Title: Notebook Engineering Intern
Location: China, Shanghai
Department: GPU

Job Description:

• Bring up of next generation Notebook GPU ASICs.
• Characterization of next generation Notebook GPU ASICs.
• High speed bus signal integrity debug/characterization.
• Troubleshooting and silicon debug.

Requirement:

• Student will graduate in 2012 is preferred.
• Team player with good communication and problem-solving skills.
• Programming skills in C and/or Perl.
• Strong understanding of IO interfaces such as PCI-Express, TMDS, LVDS, DDR1,2,3 a plus.
• Low power ASIC design understanding.
• Understanding of BIOS, drivers and other software applications.
• Experience with digital logic design, analog design is a plus.